1. Field of the Invention
The present invention relates generally to integrated circuit fabrication and, more particularly, to the inspection of semiconductor wafers.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled circuits are used in a wide variety of applications. Such applications include personal computers, control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device coupled to the microprocessor.
The devices used in typical microprocessor controlled circuits are usually formed on a semiconductor die and placed in a package. Many such devices are packaged for surface mounting. Fine-Pitch Surface Mount Technology (FPT) and Pin Grid Array (PGA) technology are well developed areas of this type of packaging technology. In addition, an emerging packaging method has been developed using Ball Grid Array (BGA) technology.
A BGA semiconductor package generally includes an integrated circuit (I/C) chip mounted on the upper surface of a substrate. The I/C chip may be electrically coupled to the substrate by bonding wires or conductive paste, for example. The substrate contains conductive routing which allows the signals to pass from the I/C chip on the upper surface of the substrate, through the substrate, and to pads on the underside of the substrate. A plurality of solder balls are deposited and electrically coupled to the pads on the underside of the substrate to be used as input/output terminals for electrically connecting the substrate to a printed circuit board (PCB) or other external device.
The packaging of electrical circuits is a key element in the technological development of any device containing electrical components. A single I/C device is typically encapsulated within a sealed package to be mounted on a PCB or another suitable apparatus for incorporation into a system. The I/C package is generally encapsulated within a molding compound to protect the die from external contamination or physical damage. The encapsulated package also provides a system of interconnects for electrically coupling the package to a PCB or other external device.
Three common techniques for mounting an I/C chip on a substrate include Chip-on-Board (COB), Board-on-Chip (BOC), and Flip-Chip (F/C). In a COB package, the I/C chip may be attached to the substrate xe2x80x9cface-up.xe2x80x9d That is to say that the side of the I/C chip containing the bond pads for wire bonding the chip to the substrate is left exposed. This side is often referred to as the upper surface of the chip. The backside of the I/C chip not containing the bond pads is adhered to the substrate. In this type of package, bona wires are attached from the upper surface of the I/C chip and to pads on the upper surface of the substrate to electrically couple the I/C chip to the substrate. The substrate contains electrical routing which routes the signals from the upper surface of the substrate to the underside of the substrate.
Alternately, the I/C chip may be mounted on the substrate xe2x80x9cface-downxe2x80x9d to create a BOC package. In this instance, the substrate typically contains a slot. Since the I/C chip is mounted face down, the bond pads on the upper surface of the chip are arranged to correlate with the slot opening in the substrate. Bond wires are attached from the bond pads on the chip, through the slot in the substrate, and to the underside of the substrate. The substrate contains electrical routing to distribute electrical signals along the back side of the substrate.
For F/C packages, the I/C chip is mounted on the substrate face-down, as in the BOC package. For a F/C package, bond wires are not used to electrically couple the I/C chip to the substrate. Instead, solder bumps located on the face of the chip are aligned with conductive pads on the upper surface of the substrate. The solder bumps may be re-flowed to electrically couple the chip to the substrate. The substrate contains electrical routing to distribute electrical signals from the I/C chip along the backside of the substrate.
Regardless of whether COB, BOC, or F/C mounting techniques are used , the package is generally encapsulated in a molding compound to protect the I/C device and bond wires from external elements such as moisture, dust, or impact. A non-conductive material, such as soldermask (or solder resist), is generally disposed on the substrate to cover the conductive traces. However, ball pads and bond wire pads are typically left exposed for electrical coupling of the integrated circuit device to the substrate and for electrical coupling of the integrated circuit package to other external devices.
Disadvantageously, the low surface tension of the soldermask may not provide an adequate surface on which to adhere the molding compound. To promote adhesion, the surface tension of the soldermask may be altered by a technique such as ultraviolet (UV) bumping. By exposing the soldermask to UV radiation, the surface tension of the soldermask is generally increased, thereby promoting surface adhesion of the molding compound. However, increasing the surface tension creates another problem associated with BGA surface mounting techniques. Solder balls generally require a low surface tension soldermask to minimize bridging problems. The higher the surface tension of the soldermask which is surrounding the ball pads, the greater the likelihood of bridging between the solder balls. Thus, the variance of surface tension creates a design issue with a dichotomous solution: Increase the surface tension of the soldermask to promote adhesion of the molding compound or decrease the surface tension of the soldermask to reduce bridging between the solder balls.
The present invention may address one or more of the problems set forth above.
Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In one embodiment of the present invention, there is provided a system including processor and an integrated circuit package operatively coupled to the processor. The integrated circuit package includes: a substrate having a first surface and a second surface, the second surface configured to receive a plurality of solder balls thereon; an integrated circuit die coupled to the first surface of the substrate; a solder resist disposed on the second surface of the substrate, the solder resist having a first portion having a first surface tension and a second portion having a second surface tension, the first surface tension being higher than the second surface tension; and a molding compound disposed on the first portion of the solder resist.
In another embodiment of the present invention, there is provided an integrated circuit package including: a substrate having a first surface and a second surface, the second surface configured to receive a plurality of solder balls thereon; an integrated circuit die coupled to the first surface of the substrate; a solder resist disposed on the second surface of the substrate, the solder resist having a first portion having a first surface tension and a second portion having a second surface tension, the first surface tension being higher than the second surface tension; and a molding compound disposed on the first portion of the solder resist.
In still another embodiment of the present invention, there is provide a board comprising a substrate having a first surface and a second surface, the second surface configured to receive a plurality of solder balls thereon and a solder resist disposed on the second surface of the substrate, the solder resist having a first portion having a first surface tension and a second portion having a second surface tension, the first surface tension being higher than the second surface tension.
In yet another embodiment of the present invention, there is provided a method of manufacturing an integrated circuit package comprising the acts of: (a) providing a substrate having a first surface and a second surface, the second surface configured to receive a plurality of solder balls thereon; (b) disposing a solder resist onto the second surface of the substrate; (c) selectively raising the surface tension of the solder resist to create a first portion of the solder resist having a first surface tension and a second portion of the solder resist having a second surface tension higher than the first surface tension; (d) disposing a molding compound on the second portion of the solder resist; and (e) disposing an integrated circuit die on the first surface of the substrate.